Semiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuit

ABSTRACT

The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor integrated circuit with a reduced clock skew and a layout method in design of a semiconductor integrated circuit with a reduced clock skew.

[0002] In recent years, semiconductor integrated circuits have been on the improvements in high density integration, large scale integration and high speed performances. It is necessary that the high density integration of the semiconductor integrated circuits is realized, whist a clock skew which may cause a hold defective is reduced to improve the reliability of the semiconductor integrated circuit.

[0003] As the high density integration has been progressed with change of the design rules from 0.25 micrometers-rule through 0.18 micrometers-rule to 0.13 micrometers-rule, a difference between a maximum value and a minimum value of an interconnection delay becomes remarkable, whereby a phase difference of the clock signals, for example, a clock skew is increased. If the phase difference of the clock signals or the clock skew becomes larger than a holding value of a flip-flop circuit, then a holding defective appears on the flip-flop circuits.

[0004]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. If a clock signal delay “N” becomes lower than a sum of a delay value “L”, a first internal delay value of a first flip-flop circuit F/F1, a delay value “M”, and a second internal delay value of a second flip-flop circuit F/F2, then the holding defective appears.

[0005] The clock skew value as the difference in delay of the clock signals is presumable but only after the layout and placement have been completed. For this reason, it is possible that after an automatic layout has been completed, the clock skew value is increased to cause the holding defective on the flip-flop circuit, whereby a malfunction of the flip-flop circuit may appear.

[0006] The following has been proposed to have solved the above problem. On the basis of delay informations after the automatic layout has been completed, then change of the circuit configuration, re-study and re-execution of the automatic layout are repeated until the clock skew is reduced.

[0007]FIG. 2 is a flow chart illustrative of a first conventional circuit design method.

[0008] In a step S81, the process is started.

[0009] In a step S82, a circuit design is carried out to form a net-list.

[0010] In a step S83, layout and placement of cells are executed by use of the net-list to form real interconnection data.

[0011] In a step S84, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.

[0012] In a step S85, a circuit design operation is confirmed and further a timing and the clock skew value are also confirmed.

[0013] In a step S86, it is verified whether or not any delay adjustment is needed. If the delay adjustment is needed, then the process will back to the step S82 for changing the circuit design or the step S83 for changing the cell layout. Those automatic layout processes will be repeated until the delay adjustment is not needed. If the delay adjustment is not needed, then the process is ended in a step S87.

[0014] In Japanese laid-open patent publication No. 10-327047, a second conventional technique is disclosed. A data input terminal or a data output terminal of a flip-flop circuit is coupled with a logic cell having a flip-flop circuit and being free of any delay circuit. Subsequently, a logic simulation is executed on the basis of the layout information. A timing information as the result of the logic simulation is investigated with reference to a design specification of the semiconductor integrated circuit to verify a possibility of malfunction due to the timing variation. The logic cell is replaced by another logic cell which has a delay circuit, so that the logic cell with the delay circuit is connected to the data input or output terminal of the flip-flop circuit.

[0015] It is considered that the clock signal is supplied from the common clock input terminal to the plural flip-flop circuits. A clock tree system causes that the number of the buffer circuits between the individual flip-flop circuits and the common clock input terminal becomes the same, whereby the clock skew value is reduced.

[0016] In this case, however, it is necessary, to compensate the delay amount. A second conventional technique has been proposed. FIG. 3 is a flow chart illustrative of a second conventional circuit design method.

[0017] In a step S91, the process is started.

[0018] In a step S92, a circuit design is executed to form a let-list.

[0019] In a step S93, layout and placement of cells are executed by use of the net-list to form real interconnection data.

[0020] In a step S94, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.

[0021] In a step S95, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted.

[0022] In a step S96, on the basis of the delay value of all paths of the clock-tree, a difference between the delay value of all paths of the clock-tree and a maximum value is calculated.

[0023] In a step S97, a delay circuit, which compensates to the calculated difference between the delay value of all paths of the clock-tree and the maximum value, is selected from a delay circuit library and the delay circuit is inserted into a logic cell to form a delay circuit cell.

[0024] In a step S98, a layout of tie delay circuit cell is executed to form real interconnection data.

[0025] In a step S99, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S100.

[0026] The above first and second conventional circuit layout methods prepare individual logic cell libraries for individual paths to verify the individual delays, whereby a design turnaround time is long.

[0027] In case of the above clock tree shown in FIG. 3, the individual delay circuits, which compensate the difference between the delay value of all circuits of the clock tree and the maximum value, is inserted into the logic cell connected to the data input or output terminal of the flip-flop circuit. There are a large number of inserting positions into which the delay circuits are inserted. In case, a layout correction is difficult. As another method, it is possible to increase the length of the interconnections so that the fast path is adjusted to a delay path. This method is, however, unavailable to the high density interconnection region.

[0028] In the above circumstances, it had been required to develop a novel layout method in design of a semiconductor integrated circuit free from the above problem.

SUMMARY OF THE INVENTION

[0029] Accordingly, it is an object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit free from the above problems.

[0030] It is a further object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit.

[0031] It is a still further object of the present invention to provide a novel method in design of a semiconductor integrated circuit to reduce a clock skew to a half of a maximum clock skew value for increasing a design efficiency and shortening a turnaround time.

[0032] It is yet a further object of the present invention to provide a novel semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit.

[0033] The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0034] The present invention also provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0035] The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings

[0037]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits.

[0038]FIG. 2 is a flow chart illustrative of a first conventional circuit design method.

[0039]FIG. 3 is a flow chart illustrative of a second conventional circuit design method.

[0040]FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention.

[0041]FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in a Accordance with the present invention.

[0042]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention.

[0043]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention.

[0044]FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7.

[0045]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention.

[0046]FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention.

[0047]FIG. 11 is a block diagram illustrative of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention.

[0048]FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11.

DISCLOSURE OF THE INVENTION

[0049] The first present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0050] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library.

[0051] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value.

[0052] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0053] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

[0054] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.

[0055] The second present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0056] It is preferable that the delay circuits are extracted from a delay circuit library.

[0057] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.

[0058] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0059] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

[0060] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted, flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.

[0061] The third present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0062] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library.

[0063] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value.

[0064] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0065] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

[0066] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.

[0067] The fourth present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.

[0068] It is further preferable that the delay circuits are extracted from a delay circuit library.

[0069] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.

[0070] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0071] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

[0072] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on: the basis of both the read interconnection data and a previously prepared delay library.

[0073] The fifth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common Clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of; the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value.

[0074] It is preferable that the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration.

[0075] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.

[0076] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0077] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

[0078] The sixth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits.

[0079] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.

[0080] It is also preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.

[0081] It is further preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.

PREFERRED EMBODIMENT FIRST EMBODIMENT

[0082] A first embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention.

[0083] In a step S11, the process is started.

[0084] In a step S12, a circuit design is executed to form a let-list.

[0085] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data.

[0086] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.

[0087] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted.

[0088] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated.

[0089] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in accordance with the present invention. The distribution of the delay value of the clock tree paths is symmetrical with reference to the average value “C” which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process.

[0090] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value.

[0091] In a step S19, clock tree paths faster than the average value are extracted.

[0092]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits.

[0093] In a step S20, a batch-replacing process is carried out, wherein the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value are substituted with substitute flip-flop circuits with delays which compensate to a difference between the average value and the maximum value. The substitute delay flip-flop circuits are selected from a previously prepared delay flip-flop circuit library.

[0094]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three substituted delay flip-flop circuits 41A. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three substituted delay flip-flop circuits 42A. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three substituted delay flip-flop circuits 43A. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three substituted delay flip-flop circuits 44A. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 7, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three substituted delay flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three substituted delay flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three substituted delay flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three substituted delay flip-flop circuits 44A. The three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A are the same as each other in delay amount. Each of the three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A has the same circuit configuration. FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7. Each of the substituted delay flip-flop circuits 41A, 42A, 43A and 44A comprises a flip-flop circuit region and a delay circuit region, wherein the flip-flop circuit region comprises series connections of plural flip-flop circuits and the delay circuit region comprises series connections of plural delay circuits. Each of the flip-flop circuits comprises a pair of first and second inverter circuits, wherein an input terminal of the first inverter circuit is connected to an output terminal of the second inverter circuit, and further an output terminal of the first inverter Circuit is connected to an input terminal of the second inverter circuit. Each of the delay circuits comprises a pair of an inverter circuit and a capacitance, wherein the capacitance is connected between an output terminal of the inverter and a ground line. The series connection of the plural delay circuits is provided on the pre-stage of the series connection of the flip-flop circuit.

[0095]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention. The delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This ½-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained.

[0096] In a step S21, layout of the substitute delay flip-flop circuit cells is carried out to prepare real interconnection data.

[0097] In a step S22, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S23.

[0098] As described above, in accordance with the first novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-substitution process is carried out for batch-substituting all flip-flop circuits connected to the extracted clock tree paths into substitute delay flip-flop circuits which have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-substitution process results in a reduction in the number of the processes for obtaining the reduced clock skew.

SECOND EMBODIMENT

[0099] A second embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention.

[0100] In a step S11, the process is started.

[0101] In a step S12, a circuit design is executed to form a let-list.

[0102] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data.

[0103] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.

[0104] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted.

[0105] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated.

[0106] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. As shown in FIG. 5, the distribution of the delay value of the clock tree paths is symmetrical with reference to the average value “C” which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process.

[0107] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value.

[0108] In a step S19, clock tree paths faster than the average value are extracted.

[0109] As shown in FIG. 6, a clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer, circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits.

[0110] In a step S30, a batch-insertion process is carried out, so that insertion delay circuits are inserted onto previous stages of the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value, wherein the insertion delay circuits have a delay which compensates to a difference between the average value and the maximum value. The insertion delay circuits are selected from a previously prepared delay circuit library.

[0111]FIG. 11 is a block diagram illustrative Of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 41A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 41A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three extracted flip-flop circuits 42A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 42A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 42A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three extracted flip-flop circuits 43A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 43A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 43A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three extracted flip-flop circuits 44A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 44A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 44A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 11, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 and the delay circuit 40 to the three extracted flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 and the delay circuit 40 to the three extracted flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 and the delay circuit 40 to the three extracted flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 and the delay circuit 40 to the three extracted flip-flop circuits 44A. The delay circuits 40 are the same as each other in delay amount. Each of the delay circuits 40 has the same circuit configuration. FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11. Each of the delay circuits 40 comprises series connections of plural pairs of inverters and capacitors, wherein the capacitor is connected between an output terminal of the inverter and a ground line. The series connection of the plural sets of the inverters and capacitors is provided on the pre-stage of the flip-flop circuit.

[0112] As shown in FIG. 9, the delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This ½-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained.

[0113] In a step S31, layout of the flip-flop circuit cells is carried out to prepare real interconnection data.

[0114] In a step S32, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S33.

[0115] As described above, in accordance with the second novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-insertion process is carried out for batch-inserting, inserting delay circuits onto a previous stage of all of flip-flop circuits connected to the extracted clock tree paths, wherein the inserting delay circuits have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-insertion process results in a reduction in the number of the processes for obtaining the reduced clock skew.

[0116] Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention. 

What is claimed is:
 1. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.
 2. The method as claimed in claim 1 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library.
 3. The method as claimed in claim 1 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value.
 4. The method as claimed in claim 3 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 5. The method as claimed in claim 4 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.
 6. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.
 7. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than: the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.
 8. The method as claimed in claim 7 , wherein the delay circuits are extracted from a delay circuit library.
 9. The method as claimed in claim 7 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.
 10. The method as claimed in claim 9 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 11. The method as claimed in claim 10 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.
 12. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.
 13. A computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.
 14. The computer program as claimed in claim 13 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library.
 15. The computer program as claimed in claim 13 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value.
 16. The computer program as claimed in claim 15 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 17. The computer program as claimed in claim 16 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.
 18. The computer program as claimed in claim 13 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.
 19. A computer program for layout processes in design for a semiconductor integrated circuit having clock free paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.
 20. The computer program as claimed in claim 19 , wherein the delay circuits are extracted from a delay circuit library.
 21. The computer program as claimed in claim 19 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.
 22. The computer program as claimed in claim 21 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 23. The computer program as claimed in claim 22 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.
 24. The computer program as claimed in claim 19 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library.
 25. A semiconductor integrated circuit having a common clock input terminal, plural Slip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value.
 26. The semiconductor integrated circuit as claimed in claim 25 , wherein the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration.
 27. The semiconductor integrated circuit as claimed in claim 25 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.
 28. The semiconductor integrated circuit as claimed in claim 27 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 29. The semiconductor integrated circuit as claimed in claim 28 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value.
 30. A semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits.
 31. The semiconductor integrated circuit as claimed in claim 30 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value.
 32. The semiconductor integrated circuit as claimed in claim 31 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value.
 33. The semiconductor integrated circuit as claimed in claim 32 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 